Phase locked loops (PLLs) have been used extensively in analog electrical systems and communication systems. In today's high performance systems operating within increasingly stringent timing constraints, PLLs are being introduced in more general digital electronic circuits. For example, application specific integrated circuits (ASICs) are used in a variety of circuit applications typically include on-chip PLLs for clock signal distribution.
The key advantages that PLLs bring to clock distribution are phase/delay compensation, frequency multiplication and duty cycle correction. A PLL enables one periodic signal or clock to be phase-aligned to and/or frequency multiples of a reference clock. As the name implies, the output of the PLL locks onto the incoming reference clock signal and generates a periodic output signal with a frequency equal to the average frequency of the reference clock. When the output PLL signal tracks the reference signal, the PLL is said to be “locked.”
A PLL, however, will only remain locked over a limited frequency range or shift in frequency called a hold-in or lock range. The PLL generally tracks the reference signal over the lock range, provided the reference frequency changes slowly. This maximum “locked sweep rate” is the maximum rate of change of the reference frequency for which the PLL will remain locked. If the frequency changes faster than this rate, the PLL will drop out of lock.
Other factors may cause loss of lock that may occur unexpectedly and suddenly. For example, single event transients caused by particle radiation (not uncommon in aerospace applications) may disrupt the PLL circuit and cause loss of lock. Integrated circuits used in space, weapons, or aviation applications are more likely to be exposed to such charged particle radiation. Solid-state integrated circuits can be vulnerable to disturbances caused by a single, charged particle. Particle-induced circuit disturbances are random and are commonly referred to as single-event effects (SEEs). SEEs can take on many forms. If the particle strike results in a bit flip or other form of corruption of stored data, this is known as a single-event upset (SEU), or a soft error. If the particle causes a transient voltage disturbance on a node of a logic circuit, this is known as a single-event transient (SET). If the node is in a clock network, a temporary voltage disturbance on a circuit node can generate a false clock pulse in a portion of the system. If undetected, loss of lock may disrupt and interfere with circuit operation.
To detect a loss of lock, lock detectors are utilized. Lock detectors typically monitor the reference clock and the PLL output to compare the frequencies of the two signals. If the frequencies match, the PLL is determined to be locked. Unfortunately, conventional lock detect circuits have several drawbacks. One drawback is that typical lock detect circuits may not indicate the disruption of the reference clock. The reference clock can be disrupted for a number of cycles by, for example, a SEU. Conventional lock detection schemes, however, do not detect transient loss of the reference clock. Disruptions that occur for only a few clock cycles may not give a lock detector enough time to detect that a clock has been disrupted. In some instances, this slow response may be attributed to a filter within a lock detector that is used to reduce noise or “jitter” in a lock detect signal.
Although the use of filtering techniques may be useful in creating a steady lock detect output, the filtered signal increases the lock detect signal response time. For example, if a SET occurs, a reference clock may only be disrupted for a few clock cycles. In a few clock cycles, only a small amount of charge may discharge from the filter within a lock detector before the reference clock recovers and the filter begins to accumulate charge again. A SET, or other transient event, may not have been detected despite its actual occurrence.
In addition, some lock detect circuits will not detect a transient loss or even a total loss of reference clock, particularly if the lock detect circuit employs logic that evaluates the PLL derived clock and not the reference clock. In this case, the lock detect signal will correspond to a lock condition when a PLL clock may not even be generated. In some cases, lock detect circuits that lose a reference clock may continue to produce a PLL clock output. A clock output may continue to increase or decrease in frequency until a voltage controlled oscillator (VCO) within the PLL is pinned at a low or high frequency that may be outside the operating range of circuits using the PLL clock output. If a PLL clock output deviates outside of normal operating range, undesirable results may occur in the circuits using the PLL clock output.
Furthermore, another disadvantage to conventional lock detect circuits is that they cannot identify small deviations in phase misalignment. Typically, lock detectors cannot identify phase misalignment until they approach the order of 60 degrees or more. For integrated circuit applications that require phase synchronization, not detecting phase alignment may also be detrimental.
Overall, as discussed above, conventional lock detectors fail in three primary areas: failure to account for rapid loss and recovery of a lock signal, loss of reference clock, or phase error. Not accounting for these factors in PLLs may cause errors in an integrated circuit device. For example, a SEU disruption in a PLL generated clock cycle may cause an error condition in a timing cell within an ASIC. The ASIC may malfunction and the cause of the error may not be corrected without causing the ASIC itself to be reset. Performing a reset of the entire ASIC could be detrimental to systems relying on the ASIC, including the systems used in the applications identified above (e.g., Space, weapons, or aviation applications). However, if the PLL generated clock cycle was designed to detect SET or SEU errors, a feedback signal from a lock detect circuit could reset the timing device within the ASIC and avoid resetting the entire ASIC. The ASIC could then continue operating in a desired manner, thereby avoiding a detrimental impact to applications that rely on the ASIC. Thus, there is a need for an improved PLL lock detector.